1. Field of the Invention
The present application relates to a phase shift keying (PSK) demodulator and, more particularly, to a PSK demodulator using a time-to-digital converter capable of a low level of power consumption and simple implementation.
2. Description of the Related Art
The related art PSK demodulator includes an I/Q analog-to-digital converter and a digital signal processor, in which a received PSK signal is converted into a digital signal via the I/Q analog-to-digital converters and the digital signal is then demodulated by the digital signal processor.
However, the I/Q analog-to-digital converter consumes large amounts of power and contains complicated circuitry, resulting in an increase in overall power consumption of the related art PSK demodulator and complicating the implementation of the PSK demodulator.
In an effort to solve the problem, a frequency shift keying (FSK) demodulator using a delay locked loop (DLL), a PSK demodulator using a period-width detector, and the like, have been proposed. However, these demodulators must necessarily have a synchronization circuit for synchronizing a PSK signal and a clock signal. Therefore, the proposed demodulators also have the same problem: increased power consumption and a complicated implementation process due to the presence of the synchronization circuit.